The enclosed tests have been collected from a number of sources and are
intended to be used as a validation suite for any toolset supporting the
language documented in the IEEE Standard VHDL Language Reference Manual
1076-1987.

Tests included within are subdivided into three broad testing categories:

    o Correct Tests - tests used for testing the support of valid language 
      features.  These tests should correctly compile and simulate, and in
      general are self checking.

    o Static Error Tests - tests used for verifying that invalid language
      features which typically can be detected by VHDL compilers are caught.
      These tests are not intended to be simulated.

    o Benchmark Tests - a series of benchmarks which may be used for
      determining capacity and performance estimates on a particular
      VHDL toolset implementation.


This tape is organized into 3 main subdirectories:

    o doc - contains text files describing the validation tests/objectives
      and procedures for running the test suite.
            
    o tests - further subdivided into the directories "bench", "correct",
      and "staterr" which contain the test files for the benchmark, correct,
      and static error tests respectively.

    o tools - contains command files for running the validation suite.


Any questions or problems which are specific to the benchmark tests should
be directed to:

        Capt Karen Serafino
        WRDC/ELED
        Wright-Patterson AFB
        Dayton, OH  45433-6543
        (513)255-8635


All other questions or problems should be directed to:

        Pam Stearman
        Intermetrics, Inc.
        4733 Bethesda Ave, Suite 415
        Bethesda, MD  20814
        (301)657-3775
        


