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| nnARM synthesizeable soft core
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| Project Name: nnARM
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Introduction 1.Purpose of this project This project has two primary purposes: FIRST: To develop a synthesizable embedded processor soft core. SECOND: To give the project members experience in organizing a free hardware development team over the internet. The GNU and Linux successes have proven that this development mode is successful for software, we want to prove it is also suitable for hardware development. 2.What help do we want? Currently, this is a very small team. There is only one main developer, and one documentation person. We can not imagine that such a small team can manage to create this entire system without additional design and testing help. So any kind of help is welcomed. If you are interest in this, please contact First, this team is particularly weak in the design of cache and memory controllers, so we are eager for help in this field. Second, we want to add support for wishbone or AMBA bus interfaces Third, peripherals like: DMA, timer, UART and many many other devices need integration into the design. Fourth: Help to test the core, both in the simulator or on an actual FPGA board. 3.What it can do and can not do now Currently, this core can support the following kinds of instructions: 1 All ALU instructions(including those instructions with PC as their source and destination) 2 Multiply and Multiply with Accumulate (The documentation from ARM states that the PC is never used as a source or destination for these instructions) 3 PSR transfer instructions. 4 Single data transfer instructions. (load/store, including those with PC as source and destination.) 5 Branch 6 SoftWare interrupt 7 Thumb instructions(NOTE:decode into normal ARM instructions, so some instruction can not be run now) The conditional execution field in the most significant 4 bits is also supported for all these instructions. An instruction prefetch buffer has been implemented between the instruction cache and IF pipeline stage. The pipeline is interlocked; if a stage is stalled, then all stages before it stall too, but all stages following it continue to run. All six operational modes of ARM are supported by the current release. All 31 general purpose registers are in a register file, and a set of registers can be accessed depending on the mode of the processor. All six PSR registers are in a separate PSR register file. Pipeline forwarding is also implemented in the pipeline. If an instruction n uses register Rn as its destination and the instruction following it uses Rn as its source, then n will redirect its result directly to n+1. The core currently can not support the following instructions: 1 Single data swap 2 Block data transfer 3 All coprocessor instructions 4 Multiple long and Multiple-Accumulate long 5 Half word transfer Also, it does not support DMA, timer, uart and the interrupt arbitrator And it does not support interrupt and exception handling. The most serious problem of the current release is that its memory and cache controller is not well organized and does not support any kind of bus interface such as WISHBONE or AMBA. 4.Books used as reference works: 1.Books on architecture Computer Architecture : A Quantitative Approach by John Hennessy, David Patterson(January 1996). 2.Books on RTL design and synthesis HDL chip design by Douglas J Smith 5.Tools in use on the project: 1. simulation tools VCS verilog simulator from workview office Verilog-XL simulator from cadence ModelSim Xilinx Edition 2.RTL synthesis tools Aurora from workview office Design Compiler from synopsys 3.ARM development tools ARM SDT 2.5 from ARM GCC for ARM. |

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