Filename : SN54xx251_notes.txt

Applicable Files (listed in order of analysis):  

IEEE/std_logic_1164.pkg.vhd  -- 9-state logic system

STD_PACK/MISC_FUNC.vhd       -- miscellaneous functions
STD_PACK/TIME_FUNC.vhd       -- timing functions
STD_PACK/SIMFLAG_.vhd        -- simulation flag declarations
STD_PACK/SIMFLAG.vhd         -- simulation flag assignments
STD_PACK/TTL_TIMING.vhd      -- environmental derating coefficients

STD_WAVES/STANDARD/waves_system.vhd    -- describes Event Value objects
STD_WAVES/STANDARD/waves_standard.vhd  -- basic WAVES definition
STD_WAVES/LOCAL/waves_events.vhd       -- links events to logic values
STD_WAVES/STANDARD/waves_interface.vhd -- defines functions for application of
                                          input values and file input of vectors

waves_device_SN54xx00.vhd              -- test pins package
STD_WAVES/LOCAL/waves_frames.vhd       -- links event values to pin codes
STD_WAVES/STANDARD/waves_objects.vhd   -- defines functions that create slices
STD_WAVES/LOCAL/waves_utilities.vhd    -- defines functions to check responses
                                          and to output port values to a file

wgenerator_SN54xx00.vhd      -- WAVES test program
SN54xx00_timing.vhd          -- timing package
SN54xx00_TB.vhd              -- test bench entity/architecture
SN54xx00.vhd                 -- entity/architecture
SN54xx00_DIP14.vhd           -- structural entity-architecure for
                                physical package
SN54xx00_TB_CON.vhd          -- top level configuration of TEST BENCH



Revision History (by file):  


+--------------------------------------------------------------------+
| All files:                                                         |
+--------------------------------------------------------------------+
Version 2.1 updates

1-09-91  / G. Newell /
  Converted to IEEE MVL-9 state/strength value system (Std_Ulogic)
  Adopted consistent file naming convention: 
    Entities and package declarations end in "_.vhd"
    Architectures and package bodies end in ".vhd"

2-08-91  / S. Turner /
  SIMFLAG package is now in STD_PACK library
  New convention for capitalization:
    ALL CAPS :  variables, constants, functions, design units
    First_Cap:  type definitions
    all_lower:  reserved VHDL keywords

12-19-90 / G. Newell / 
  Version 1.1 created

+--------------------------------------------------------------------+
| SN54xx251.vhd                                                       |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx251

08-08-91    / M. Meier /
  changed POWER to VCC-GND

08-08-91    / S. Turner /
  returned by / M. Meier / without comments

08-02-91    / M. Meier /
  changed local output signal type to UX01Z.

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164
  made architecture  only one process

07-23-91    / S. Turner /
  new timing module changes

07-15-91    / C. Collins /
  moved comments to DIP file

07-08-91    / S. Turner /
  fixed syntax error

2-08-91  / S. Turner /
  Changed parameter names to reflect changed in entity's generic map
  Added to the generic map:
    SIMFLAG parameters
    Default propagation delay times
    INITIAL_OUTPUTS
  Moved notes and comments into this file (SN54xx251_notes.txt)

1-09-91  / G. Newell /
  Replaced "Filter2" with "CONVERT_TO_UX01" (same purpose)
  Added assertion warning for illegal state on POWER input
  POWER input added to sensitivity list of behavioral processes
  Output signals default to INITIAL_OUTPUTS[]
  Added POWER input
  Reference designator now defaults to name of the device
  Output pins now default to INITIAL_OUTPUTS array.


+--------------------------------------------------------------------+
| SN54xx251_timing.vhd                                                |
+--------------------------------------------------------------------+
Version 2.1 updates

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file

07-28-91    / S. Turner /
  moved declaration into this file

07-16-91    / S. Turner /
  removed TIMING_PARAMS declaration

2-08-91  / S. Turner /
  Added GEN_CWIRES and GEN_PARAMS to GET_TIMING() parameter list 
  Added KCHL and KCLH capacitance derating factors for each output pin
  Added capacitance derating coefficients for CALC_CURVE()
  Added WIRE_FACTOR constant to convert wire capacitance into delay time
  Following "EIA Timing and Environmental Data Specification" guidelines to 
    calculate missing manufacturer's timing parameters
  Changed parameter names to reflect changed in entity's generic map
  Eliminated GENERIC/TIMING/ANNOTATED option -- Generic timing parameters
    are now selected with the GENERIC_VALUES option of TIME_MODE in the 
    SIMFLAG package.  Back-annotation of capacitance values occurs
    automatically when capacitances other than the default are passed in.
  All PROP_DELAYS are now multiplied by the capacitance derating factor,
    in addition to voltage and temperature factors.
  Eliminated Eflags type in favor of separate XGEN and TIMING_MESG flags
  Grouped wire and fanout capacitances into record types,
    and are referenced by pin name rather than pin number
  Manufacturer's timing parameters grouped into MIN, TYP, MAX constants
  Added record types Wire_Times, Cwire_In, Cload_Out, Timing_Params
  Changed Sim_Timing record type to contain PROP_DELAYS and WIRE_DELAYS
  Added GEN_CWIRES and GEN_PARAMS to GET_TIMING() parameter list 

+--------------------------------------------------------------------+
| SN54xx251_TB.vhd                                                    |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx251

08-08-91    / M. Meier /
  changed POWER to VCCC-GND

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164
  moved entity into this file

6/11/91    / S. Turner /  
  Version 2.1 created

+--------------------------------------------------------------------+
| SN54xx251_DIP16_.vhd                                                |
+--------------------------------------------------------------------+
Version 2.1 updates

08-08-91    / M. Meier /
  moved configuration specification from CON file to DIP file

08-08-91    / M. Meier /
  changed POWER to VCC-GND

07-29-91    / M. Meier /
  added TA nominal

07-29-91    / M. Meier /
  added recommended and worst case operating conditions

07-28-91    / S. Turner /
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164

07-15-91    / C. Collins /
  moved comments from SN54xx251_.vhd

6/11/91    / S. Turner /  
  Version 2.1 created

+--------------------------------------------------------------------+
| SN54xx251_TB_CON.vhd                                                |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx251

08-08-91    / M. Meier /
  moved configuration specification from CON file to DIP file

07-28-91    / S. Turner /
  changed library references

6/11/91    / S. Turner /  
  Version 2.1 created

+--------------------------------------------------------------------+
| waves_device_SN54xx251.vhd                                          |
+--------------------------------------------------------------------+
Version 2.1 updates

08-08-91    / M. Meier /
  changed POWER to VCC-GND

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file

07-28-91    / S. Turner /
  moved declaration into this file

6/11/91    / S. Turner /  
  Version 2.1 created

+--------------------------------------------------------------------+
| wgenerator_SN54xx251.vhd                                            |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx251

08-08-91    / M. Meier /
  changed POWER to VCC-GND and removed POWER vectors

07-30-91    / M. Meier /
  changed 'D' to '-'

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file

07-28-91    / S. Turner /
  moved declaration into this file

07-19-91    / M. Meier /
  corrected test vectors

07-19-91    / M. Meier /
  added improved test vectors

07-19-91    / M. Meier /
  added forgotton POSER_INPUT vecotrs

07-19-91    / M. Meier /
  added new timing vectors

6/11/91    / S. Turner /  
  Version 2.1 created


