Filename : SN54xx138_notes.txt

Applicable Files (listed in order of analysis):  

IEEE/std_logic_1164.pkg.vhd  -- 9-state logic system

STD_PACK/MISC_FUNC.vhd       -- miscellaneous functions
STD_PACK/TIME_FUNC.vhd       -- timing functions
STD_PACK/SIMFLAG_.vhd        -- simulation flag declarations
STD_PACK/SIMFLAG.vhd         -- simulation flag assignments
STD_PACK/TTL_TIMING.vhd      -- environmental derating coefficients

STD_WAVES/STANDARD/waves_system.vhd    -- describes Event Value objects
STD_WAVES/STANDARD/waves_standard.vhd  -- basic WAVES definition
STD_WAVES/LOCAL/waves_events.vhd       -- links events to logic values
STD_WAVES/STANDARD/waves_interface.vhd -- defines functions for application of
                                          input values and file input of vectors

waves_device_SN54xx138.vhd             -- test pins package
STD_WAVES/LOCAL/waves_frames.vhd       -- links event values to pin codes
STD_WAVES/STANDARD/waves_objects.vhd   -- defines functions that create slices
STD_WAVES/LOCAL/waves_utilities.vhd    -- defines functions to check responses
                                          and to output port values to a file

wgenerator_SN54xx138.vhd      -- WAVES test program
SN54xx138_timing.vhd          -- timing package
SN54xx138_TB.vhd              -- test bench entity/architecture
SN54xx138.vhd                 -- entity/architecture
SN54xx138_DIP14.vhd           -- structural entity-architecure for
                                 physical package
SN54xx138_TB_CON.vhd          -- top level configuration of TEST BENCH


Revision History (by file):  

+--------------------------------------------------------------------+
| All files:                                                         |
+--------------------------------------------------------------------+
Version 2.1 updates

2-08-91  / S. Turner /
  SIMFLAG package is now in STD_PACK library
  New convention for capitalization:
    ALL CAPS :  variables, constants, functions, design units
    First_Cap:  type definitions
    all_lower:  reserved VHDL keywords

+--------------------------------------------------------------------+
| SN54xx138.vhd                                                       |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx138

08-06-91    / S. Turner /
  changed POWER to VCC-GND, fixed test vectors

08-02-91    / M. Meier /
  changed local output signal type to UX01Z.

08-02-91    / M. Meier /
  changed GIN1, GIN2A, GIN2B, AIN, BIN, CIN signal types to UX01

07-30-91    / M. Meier /
  changed not(POWER ... to BIT_UNKNOWN(POWER)

07-29-91    / S. Turner /
  changed 'D' to '-'

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164

07-15-91    / C. Collins /
  moved comments to DIP file

07-19-91    / M. Meier /
  added 'L' and 'H' states to POWER cases

2-08-91  / S. Turner /
  Changed parameter names to reflect changed in entity's generic map

1-09-91  / G. Newell /
  Replaced "Filter2" with "CONVERT_TO_UX01" (same purpose)

+--------------------------------------------------------------------+
| SN54xx138_timing.vhd                                                |
+--------------------------------------------------------------------+
Version 2.1 updates

08-06-91    / S. Turner /
  corrected STD Family -- not available

2-08-91  / S. Turner /
  Added GEN_CWIRES and GEN_PARAMS to GET_TIMING() parameter list 
  Added KCHL and KCLH capacitance derating factors for each output pin
  Added capacitance derating coefficients for CALC_CURVE()
  Added WIRE_FACTOR constant to convert wire capacitance into delay time
  Following "EIA Timing and Environmental Data Specification" guidelines to 
    calculate missing manufacturer's timing parameters
  Changed parameter names to reflect changed in entity's generic map
  Eliminated GENERIC/TIMING/ANNOTATED option -- Generic timing parameters
    are now selected with the GENERIC_VALUES option of TIME_MODE in the 
    SIMFLAG package.  Back-annotation of capacitance values occurs automatically
    when capacitances other than the default are passed in.
  All PROP_DELAYS are now multiplied by the capacitance derating factor,
    in addition to voltage and temperature factors.

+--------------------------------------------------------------------+
| SN54xx138_TB.vhd                                                    |
+--------------------------------------------------------------------+
Version 2.1 updates

08-08-91    / M. Meier /
  removed WAVES ascii chart

08-06-91    / S. Turner /
  changed POWER to VCC-GND, fixed test vectors

07-31-91    / M. Meier /
  changed OUT_FILE_NAME to "out.dat"

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164

07-15-91    / S. Turner /
updated timing module

6/11/91    / S. Turner /   
Version 2.1 created

+--------------------------------------------------------------------+
| SN54xx138_DIP16.vhd                                                 |
+--------------------------------------------------------------------+
Version 2.1 updates

08-08-91    / M. Meier /
  moved configuration specification from CON file to DIP file

08-06-91    / S. Turner /
  corrected STD Family -- not available

08-06-91    / S. Turner /
  changed POWER to VCC-GND, fixed test vectors

07-29-91    / M. Meier /
  added TA nominal

07-29-91    / M. Meier /
  added recommended and worst case operating conditions

07-28-91    / S. Turner /
  changed STD_PACK.LOGIC_SYSTEM to IEEE.STD_LOGIC_1164

07-15-91    / C. Collins /
  moved comments from SN54xx138_.vhd file

07-15-91    / S. Turner /
  updated timing module

6/11/91    / S. Turner /   
  Version 2.1 created

+--------------------------------------------------------------------+
| SN54xx138_TB_CON.vhd                                                |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  removed STD family since not available.

08-12-91    / M. Meier /
  changed library WORK to library SN54xx138

08-08-91    / M. Meier /
  moved configuration specification from CON file to DIP file

08-06-91    / S. Turner /
  corrected STD Family -- not available

07-15-91    / S. Turner /
  updated timing module

6/11/91    / S. Turner /   
  Version 2.1 created

+--------------------------------------------------------------------+
| waves_device_SN54xx138.vhd                                          |
+--------------------------------------------------------------------+
Version 2.1 updates

08-06-91    / S. Turner /
  changed POWER to VCC-GND, fixed test vectors

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file

6/11/91    / S. Turner /   
  Version 2.1 created

+--------------------------------------------------------------------+
| wgenerator_SN54xx138.vhd                                           |
+--------------------------------------------------------------------+
Version 2.1 updates

08-12-91    / M. Meier /
  changed library WORK to library SN54xx138

08-09-91    / M. Meier /
  replaced tabs with 4 spaces

08-06-91    / S. Turner /
  changed POWER to VCC-GND, fixed test vectors

07-30-91    / M. Meier /
  changed 'D' to '-'

07-30-91    / M. Meier /
  changed order of vectors

07-28-91    / S. Turner /
  moved entity-declarations & architecture-bodies into 1 file

07-19-91    / M. Meier /
  corrected vectors

07-19-91    / M. Meier /
  added new test vectors

6/11/91    / S. Turner /   
  Version 2.1 created

