This data item contains VHDL behavioral descriptions for 19 TTL SSI part models,
along with the functional logic package and the WAVES packages and test benches used
to simulate the models.

Contract:  MDA972-88-J-0003 

Models:
-------
  SN54xx00      quad 2-input NAND
  SN54xx02      quad 2-input NOR
  SN54xx04      hex inverter
  SN54xx08      quad 2-input AND    
  SN54xx10      triple 3-input NAND
  SN54xx109     dual JK flip-flop
  SN54xx11      triple 3-input AND
  SN54xx112A    dual JK flip-flop
  SN54xx138     3-to-8 decoder 
  SN54xx140     dual 4-input NAND
  SN54xx161A    4-bit binary counter
  SN54xx175     quad D flip-flop
  SN54xx20      dual 4-input NAND
  SN54xx21      dual 4-input AND
  SN54xx251     8-to-1 mux
  SN54xx27      triple 3-input NOR
  SN54xx280     9-bit parity generator
  SN54xx30      8-input NAND
  SN54xx32      quad 2-input OR
  SN54xx33      quad 2-input NOR w/ open-collector outputs
  SN54xx368A    hex inverting bus driver
  SN54xx38      quad 2-input NAND w/ open-collector ouptuts
  SN54xx86      quad 2-input XOR

Files common to all 23 parts:
-----------------------------
std_logic_1164.pkg.vhd     -- 9 value logic system,logical operators, etc.

MISC_FUNC.vhd              -- miscellaneous functions
TIME_FUNC.vhd              -- timing functions
SIMFLAG_.vhd               -- simulation flag declarations
SIMFLAG.vhd                -- simulation flag assignments
TTL_TIMING.vhd             -- environmental derating coefficients

waves_system.vhd           -- defines system dependent types used by WAVES
waves_standard.vhd         -- the basic WAVES definition
waves_events.vhd           -- links events to logic values
waves_interface.vhd        -- defines functions for application of input values
                              and file input of vectors 
waves_frames.vhd           -- links event values to pin codes
waves_objects.vhd          -- defines functions that create slices
waves_utilities.vhd        -- check responses, write outputs to file
  
Files specific to each model:
-----------------------------
  waves_device_<PART>.vhd  - test pins package
  wgenerator_<PART>.vhd    - WAVES test program
  <PART>_timing.vhd        - timing module package
  <PART>_TB.vhd            - test bench entity/architecture
  <PART>.vhd               - behavioral entity/architecture
  <PART>_DIP14.vhd         - structural entity/architecture for package
  <PART>_TB_CON.vhd        - top level configuration of TEST BENCH
